Equalizing driver circuits are often used in high speed signaling systems to mitigate the effects of inter-symbol interference and crosstalk. Referring to signaling system 100 of FIG. 1, for example, data values queued in buffer 104 are output to signal path 102 by output driver 101 simultaneously with transmission of an equalizing signal by equalizing driver 109. In the example shown, the equalizing driver 109 includes a shift register 113 and a bank of output drivers 111 to generate an equalizing signal based on the two most recently transmitted data values and the data value to be transmitted after the present, reference value. Thus, the equalizing driver 109 constitutes a three-tap (i.e., three data source) equalizer for reducing inter-symbol interference that results from dispersion of signals transmitted near in time to the reference value (i.e., dispersion-type ISI).
While the equalizing driver 109 is effective for reducing relatively low-latency distortions such as dispersion-type ISI, other types of systematic distortions, such as signal reflections (also referred to as reflection-type ISI), tend to have a much higher latency (i.e., occur much later in time relative to transmission of the reference value) and therefore would require a substantially larger number of taps and a correspondingly larger shift register to counteract. For example, in the system of FIG. 1, a first reflection, AT, occurs when a reference signal encounters an impedance discontinuity at a transmit-side interface 105 between a transmit-side portion (102A) and a backplane portion (102B) of the signal path 102 (e.g., a connector interface to a backplane). Because the reflection bounces between the interface 105 and the output of the transmit circuit, the reflection will arrive at the input of a receiver 103 with a latency (i.e., delay relative to arrival of the unreflected reference signal) equal to approximately twice the reflection flight time between the transmit-side interface 105 and the transmit circuit output. Impedance discontinuities at the input to receiver 103 and at a receive-side interface 107 between a receive-side portion (102C) and the backplane portion (102B) of the signal path 102 similarly produce reflections, AR, CT, CR and D that arrive at the receiver 103 at respective, latent times according to the additional distance traveled by the reflections. FIG. 2 is a waveform diagram of reflections AT, AR, B, CT, CR and D illustrating their respective latencies relative to reference signal arrival time, T (A2TR corresponds to additional reflections produced by the interface 105). Because such reflections may occur at latencies on the order of tens or even hundreds of signal transmission intervals, the shift register 113 would need to be substantially deeper in order to store the tap values needed to mitigate the resulting distortions. Moreover, the precise time at which reflections arrive at the receiver 103 are dependent upon system configuration, meaning that a generally applicable equalizer, whether implemented on the transmit or receive side of the signaling system 100, would need a relatively large number of equalizing taps to be able to compensate for a reflection occurring at any time between the signal transmit time and a worst case latency. Unfortunately, each additional equalizing tap increases the parasitic capacitance of the transmit or receive circuit, degrading the frequency response of the circuit and potentially increasing the impedance discontinuity (and therefore the magnitude of reflected signal) at the circuit input/output.